ESD Stress Effect on Failure Mechanisms in GaN-on-Si Power Device.
In: IEEE Transactions on Device & Materials Reliability, Jg. 21 (2021-12-01), Heft 4, S. 479-485
Online
academicJournal
Zugriff:
This paper reports investigation of failure mechanisms of GaN-on-Si power device under electrostatic discharge (ESD) stress using on-wafer transmission-line pulse (TLP) testing. Hot-hole injections under the gate and filament formation in the buffer layer are examined by monitoring the threshold voltage ($V_{th}$) and on-resistance ($R_{on}$) subjected to a floating gate or an off-state gate voltage. Distinct and continued degradation has been observed after the ESD stress is removed indicating a slow de-trapping process due to deep-level buffer traps. Finally, 2D device simulation is used to probe the physical insight into failure mechanisms. [ABSTRACT FROM AUTHOR]
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Titel: |
ESD Stress Effect on Failure Mechanisms in GaN-on-Si Power Device.
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Autor/in / Beteiligte Person: | Yang, Wen ; Stoll, Nicholas ; Yuan, Jiann-Shiun |
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Zeitschrift: | IEEE Transactions on Device & Materials Reliability, Jg. 21 (2021-12-01), Heft 4, S. 479-485 |
Veröffentlichung: | 2021 |
Medientyp: | academicJournal |
ISSN: | 1530-4388 (print) |
DOI: | 10.1109/TDMR.2021.3108761 |
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