Low Voltage Floating Gate MOS Transistor Based Differential Voltage Squarer.
In: ISRN Electronics, 2014, S. 1-6
academicJournal
Zugriff:
This paper presents novel floating gate MOSFET (FGMOS) based differential voltage squarer using FGMOS characteristics in saturation region. The proposed squarer is constructed by a simple FGMOS based squarer and linear differential voltage attenuator. he squarer part of the proposed circuit uses one of the inputs of two-input FGMOS transistor for threshold voltage cancellation so as to implement a perfect squarer function, and the differential voltage attenuator part acts as input stage so as to generate the differential signals. The proposed circuit provides a current output proportional to the square of the difference of two input voltages. he second order effect caused by parasitic capacitance and mobility degradation is discussed. The circuit has advantages such as low supply voltage, low power consumption, and low transistor count. Performance of the circuit is verified at ±0.75V in TSMC 0.18 μm CMOS, BSIM3, and Level 49 technology by using Cadence Spectre simulator. [ABSTRACT FROM AUTHOR]
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Titel: |
Low Voltage Floating Gate MOS Transistor Based Differential Voltage Squarer.
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Autor/in / Beteiligte Person: | Gupta, Maneesha ; Srivastava, Richa ; Singh, Urvashi |
Zeitschrift: | ISRN Electronics, 2014, S. 1-6 |
Veröffentlichung: | 2014 |
Medientyp: | academicJournal |
ISSN: | 2090-8679 (print) |
DOI: | 10.1155/2014/357184 |
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